About Me
I am a PhD graduate in Electrical and Computer Engineering from the University of Colorado Boulder, where I also earned my Master's degree. Prior to that, I received my Honors Bachelor of Science in Computer Engineering from the University of Arkansas.
My work focuses on CPU microarchitecture, performance modeling, computer architecture security, and compilers. I have developed defenses against transient execution attacks (e.g., Spectre), extended Clang/LLVM with custom instructions and compiler passes, modeled secure branch and memory prediction mechanisms in gem5, and designed FPGA-based accelerators.
Selected Highlights
- Authored peer-reviewed publications spanning CPU security, microarchitecture, compilers, secure memory, and acceleration.
- Designed and implemented novel CPU microarchitectural mechanisms in gem5, including secure branch and memory dependence predictors, load-store unit enhancements, and hardware defenses against transient execution attacks.
- Extended Clang/LLVM with custom RISC-V instructions and compiler analyses that communicate program memory behavior to hardware through ISA extensions to strengthen memory safety.
- Developed a machine-learning-based pruning strategy for Souper, a synthesis-driven superoptimizer for LLVM IR, by creating custom datasets, training predictive models in Python, and deploying the models for inference in Souper's C++ codebase using ONNX Runtime.
- Built a multi-pass Python to x86 compiler implementing parsing, liveness analysis, interference graph, graph coloring register allocation, spill code insertion, and code generation.
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Research Projects
Secure CPU microarchitecture, defenses against transient execution attacks, and FPGA-based accelerators.
Publications
Peer-reviewed work in computer architecture, secure memory, compiler optimization, and hardware acceleration.
Teaching
Teaching assistant experience in computer organization, advanced computer architecture, and digital design.
Technical Skills
Tools and expertise across CPU modeling, LLVM, gem5, FPGA design, machine learning, and systems programming.
Contact
I am interested in roles related to CPU architecture, performance modeling, compiler hardware co-design, secure processor design, and systems research.